<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Politecnico di Torino | Portfolio</title><link>https://ahsanali555.netlify.app/tag/politecnico-di-torino/</link><atom:link href="https://ahsanali555.netlify.app/tag/politecnico-di-torino/index.xml" rel="self" type="application/rss+xml"/><description>Politecnico di Torino</description><generator>Wowchemy (https://wowchemy.com)</generator><language>en-us</language><lastBuildDate>Sun, 15 Jun 2025 00:00:00 +0000</lastBuildDate><image><url>https://ahsanali555.netlify.app/media/logo_hu69593900040c7819e40edecd5a109f46_5982_300x300_fit_lanczos_3.png</url><title>Politecnico di Torino</title><link>https://ahsanali555.netlify.app/tag/politecnico-di-torino/</link></image><item><title>Digital PID Controller on STM32 NucleoF401RE for DC Motor</title><link>https://ahsanali555.netlify.app/project/apps/</link><pubDate>Sun, 15 Jun 2025 00:00:00 +0000</pubDate><guid>https://ahsanali555.netlify.app/project/apps/</guid><description>&lt;DIV align="justify">
Digital PID is designed using non-canonical form, implemented with Embedded C in STMcube IDE with Nucleo F401RE board for a Encoder based DC Motor
&lt;/DIV></description></item><item><title>Design of ARC and Pre-Focusing Unit Photonics</title><link>https://ahsanali555.netlify.app/project/ip/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://ahsanali555.netlify.app/project/ip/</guid><description>&lt;DIV align="justify">
MATLAB and OSLU EDU based Anti-Reflection Coating designs for Single Layer, Double Layer, for both Quarter and non-Quarter Wave Optical Thickness. Pre-Focusing unit design to deal with spherical aberration in case of non f-theta lens usage
&lt;/DIV></description></item><item><title>Hardware PCB Design for Smart ID System with 5C Pattern Classification</title><link>https://ahsanali555.netlify.app/project/ese/</link><pubDate>Wed, 01 Jan 2025 00:00:00 +0000</pubDate><guid>https://ahsanali555.netlify.app/project/ese/</guid><description>&lt;DIV align="justify">
OrCAD Schematics, Allegro, Presto and KiCAD based PCB design for Smart ID system as COVID application with drill and route classification of 5C
&lt;/DIV></description></item><item><title>Design, Fabrication and Testing of Low Pass Filter with AWR, AXIEM and Keysight VNA</title><link>https://ahsanali555.netlify.app/project/ges/</link><pubDate>Mon, 15 Jul 2024 00:00:00 +0000</pubDate><guid>https://ahsanali555.netlify.app/project/ges/</guid><description>&lt;DIV align="justify">
Design and Implementation of Equal Ripple 0.5dB LPF using T and Pi Networks, tested and simulated with AWR and Axiem to fabricate PCB circuit and analyzed with Keysight VNA. Medium Transmission Line models are used along with TXline tool to design the N equal 5 stage low-pass filter with length and widths tuned in order to meet the design constraint of cut-off frequency to be 2.4 GHz with IL greater than 30dB. Microstrip design techniques are further used to realize the geometrical circuit.
&lt;/DIV></description></item></channel></rss>